Strain engineering is employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel.
In CMOS technologies, PMOS and NMOS respond differently to different types of strain. Specifically, PMOS performance is best served by applying compressive strain to the channel, whereas NMOS receives benefit from tensile strain. SiGe (Si1-xGex), consisting of any molar ratio of silicon and germanium, is commonly used as a semiconductor material in integrated circuits (ICs) as a strain-inducing layer for strained silicon in CMOS transistors.
Strained silicon is a layer of silicon in which the silicon atoms are stretched beyond their normal inter atomic distance. This can be accomplished by putting the layer of silicon over a substrate of silicon germanium (SiGe), for example. As the atoms in the silicon layer align with the atoms of the underlying silicon germanium layer, which are arranged farther apart with respect to those of a bulk silicon crystal, the links between the silicon atoms become stretched—thereby leading to strained silicon.
Currently, the PMOS strain is realized by undercutting the source/drain area and epitaxially growing SiGe film in the undercut region. The larger lattice constant of the SiGe film provides the uniaxial strain to the Si channel. The higher the Ge concentration, the larger the strain and thus better performance. However, the Ge incorporation into the SiGe film is limited by the epitaxial process. Very high Ge concentration SiGe film is difficult to realize using the conventional epitaxial method, which is extremely sensitive to surface preparation, pre-cursors used and growth conditions. It is challenging to meet the ever-increasing Ge concentration requirement and maintain proper control of the SiGe profile for the SiGe source/drain (S/D) in PMOS with epitaxial growth.